1. Field of the Invention
The present invention relates to an analog-to-digital (A/D) converter, and more particularly, to a low-voltage A/D converter which improves resolution by applying a sampling block at input terminal of a comparator to 0.about.Vdd period.
2. Discussion of the Related Art
Generally, industrial systems and controllers have trends to digital with the spread of CPUs having fast speed in an analog circuit at suitable cost. Most of industrial systems and controllers share digital mode with analog mode. In this respect, for signal transmission between digital mode and analog mode, analog-to-digital converter or digital-to-analog converter is required.
An analog-to-digital (A/D) converter is divided into an integrated mode and a comparative mode depending on a conversion mode. Since the comparative mode has a conversion speed faster than the integrated mode, it is mainly used in image processors and the like which require high conversion speed.
A background art A/D converter will be described with reference to the accompanying drawings.
FIG. 1 is a circuit diagram illustrating a background art flash A/D converter. FIG. 2 is a block diagram illustrating a background art comparator. FIG. 3 is a circuit diagram illustrating a background art NMOS transistor sampling block.
As shown in FIG. 1, a background art 4-bit flash A/D converter includes data input/output terminals consisting of a positive reference voltage input terminal 3 for inputting a positive reference voltage VREFP, a negative reference voltage input terminal 4 for inputting a negative reference voltage VREFN, a positive value input terminal 6 for inputting a positive input value INP, a negative value input terminal 5 for inputting a negative input value INN, and a digital data output terminal 7, resistors R1.about.R16 connected in series to sequentially level down the positive reference voltage and the negative reference voltage VREFN input through the data input/output terminals, comparators 2a.about.2o for respectively comparing the positive reference voltage VREFP and the negative reference voltage VREFN leveled down by the resistors R1.about.R16 at a certain unit with the positive input value INP and the negative input value INN, and an encoder 1 for encoding the resultant value output from the comparators 2a.about.2o and outputting the digital converted value.
In the 4-bit flash A/D converter of FIG. 1, the number of the comparators is 2.sup.4 -1.
Each of the comparators includes a sampling block 8 for respectively sampling the positive reference voltage VREFP and the negative reference voltage VREFN leveled down by the resistors R1.about.R16 at a certain unit, the positive input value INP and the negative input value INN, an amplifier 9 for amplifying the sampled value, and a latch 10 for latching the positive value and the negative value output from the amplifier 9.
The sampling block 8 of the comparator will be described with reference to FIG. 3.
The sampling block 8 includes NMOS transistors NM1 and NM4 for switching the positive input value INP and the negative input value INN by an input operation clock PH1, NMOS transistors NM2 and NM3 for switching the positive reference voltage VREFP and the negative reference voltage VREFN by an operation clock PH2, capacitors C1 and C2 for storing and outputting sampling voltage values depending on selective turn-on/off of the NMOS transistors NM1, NM2, NM3 and NM4, and NMOS transistors NM5 and NM6 turned on by applying an operation clock PH3 at high to maintain output terminal of the sampling block 8 at AGND (ground) level and turned off by applying the operation clock PH3 at low after sampling operation is completed, for outputting sampling values.
The sampling block 8 performs sampling operation by externally applied operation clocks PH1, PH2 and PH3 as follows.
If the operation clock PH2 is applied at high under the state that the positive input value INP1 and the negative input value INN1 are maintained at AGND(ground) level by the operation clock PH3, the negative reference voltage VREFN and the positive reference voltage VREFP leveled down by the resistors R1.about.R16 are sampled as follows. EQU INN1=VREFN-AGND EQU INP1=VREFP-AGND
Subsequently, if the operation clock PH1 is applied at high and the operation clock PH2 is applied at low, the input voltages INN and INP are sampled. EQU INN1=INN-(VREFN-AGND) EQU INP1=INP-(VREFP-AGND)
INN1 and INP1 sampled by the sampling block 8 are amplified through the amplifier 9 and output as digital values through the latch 10.
The digital values sampled, amplified and latched in each of the comparators 2a.about.2o are encoded by the encoder 1 and finally output as 4 bits.
Since the background art flash A/D converter includes the sampling block consisting of only NMOS transistors, it has several problems.
Input range of the NMOS transistor is 0.about.(Vdd-V.sub.T). In the current trend to low voltage of systems, it is impossible to use high input range by high V.sub.T, so that resolution of the A/D converter is deteriorated.